Using Twisted-Ring Counters*

(C) 2001 OPA (Overseas Publishers Association) N.V. Published by license under the Gordon and Breach Science Publishers imprint, of member the Taylor & Francis Group.

VLSI DESIGN 2001, Vol. 12, No. 4, pp. 475-486 Reprints available directly from the publisher Photocopying permitted by license only

Efficient Test Application for Core-Based Systems Using Twisted-Ring Counters* ANSHUMAN CHANDRA a’t, KRISHNENDU CHAKRABARTY and MARK C. HANSENb aDepartment of Electrical and Computer Engineering, Duke University, 130 Hudson Hall, Box 90291, bDelphi Delco Electronics Systems, IC Design Center, 2705 Goyer Road, P.O. Box 9005,

Durham, NC 27708;

Mail Station D18, Kokomo, IN 46904-9005

(Received 15 August 1999; In finalform 11 September 2000)

We present novel test set encoding and pattern decompression methods for core-based systems. These are based on the use of twisted-ring counters and offer a number of important advantages-significant test compression (over 10X in many cases), less tester memory and reduced testing time, the ability to use a slow tester without compromising test quality or testing time, and no performance degradation for the core under test. Surprisingly, the encoded test sets obtained from partially-specified test sets (test cubes) are often smaller than the compacted test sets generated by automatic test pattern generation programs. Moreover, a large number of patterns are applied test-per-clock to cores, thereby increasing the likelihood of detecting non-modeled faults. Experimental results for the ISCAS benchmark circuits demonstrate that the proposed test architecture offers an attractive solution to the problem of achieving high test quality and low testing time with relatively slower, less expensive testers. Keywords: Embedded core testing; Slower-speed testers; Test set encoding; Test rate; Test vector decompression; Test-per-clock

1. INTRODUCTION

design changes, thereby affecting time-to-market. Unfortunately, the testing time for a core-based system can be very high due to the fact that the test patterns for the embedded cores are applied serially via scan chains. In such test-per-scan methods, one test pattern is applied to an n-input core under test every n cycles. For embedded cores that use the same internal scan chain for applying

System-on-a-chip designs containing embedded cores pose a number of difficult test challenges [1]. One of these involves the reduction of test application time. Testing time is especially important for a core-based system since long test times can significantly increase cost and require

* This research was supported in part by the National Science Foundation under grant no. 9875324, by a contract from Delphi Delco Electronics Systems, and by an equipment grant from Sun Microsystems. Corresponding author. Tel.: (919) 660-5230, Fax: (919) 660-5293, e-mail: [email protected] 475

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test patterns and capturing test responses, such serialization of the test patterns is unavoidable. However, a test-per-scan method increases the testing time unnecessarily for a core that employs a boundary scan chain for test application, and uses a separate circuit for capturing test responses. While parallel access to the core in such cases is possible by multiplexing the core I/Os to chip I/Os [2], the routing and area overhead associated with such a test access mechanism can be prohibitive. The testing time for a core-based system can be reduced by employing built-in self-test (BIST). However, BIST for logic cores is feasible only if the core vendor provides "BIST-able cores". Another problem in using BIST for core testing lies in the fact that practical (low-cost) pattern generation methods that provide high fault coverage require structural information about the IP core, either for test-point placement [3], or for carrying out fault simulation and ATPG [4]. The core vendor usually provides only a precomputed test set for the core. In order to reduce the testing time for "nonBIST-able cores", a recently proposed test vector compression/decompression method that uses an on-chip decoder and a cyclical scan register to apply a precomputed test set T to the core [5]. Test vectors provided by the core vendor are stored in compressed form in the tester memory, and transferred serially to the core and decompressed during test application. However, a problem with this method is that it is based on a test-per-scan architecture and is therefore inefficient for cores containing boundary scan registers that do not capture test responses. In this paper, we introduce a new test compression/decompression method based on the use of twisted-ring (Johnson) counters (TRCs) [6]. Unlike the BIST method presented in [6], the test application method described here does not require reseeding of the twisted-ring counter. For cores containing boundary scan, a test-per-clock architecture allows the application of a test pattern to the core every clock cycle. It imposes no performance penalty beyond what is introduced

by scan design. Since a larger number of patterns are applied to the CUT every cycle, the proposed test set-up can also be used with a slower-speed tester without affecting test quality. It is becoming increasingly difficult for testers to keep up with the high frequencies needed to sufficiently test for performance-related defects in today’s IC’s. Highspeed testers also pose greater interfacing problems during test. Moreover, the SIA National Technology Roadmap predicts that the cost of high-speed testers will exceed $20 million by 2010 [7]. Hence, test methods that can be used with slower-speed, less expensive testers are becoming especially important [8]. In contrast to a conventional test-per-scan method, the proposed method applies patterns to the core at every clock cycle, hence the test responses must be observed every clock cycle. We also show that the proposed compression method is flexible in that the TRC-based test can be designed using both fully-specified and partiallyspecified test sets. Finally, we compare the size of the encoded test sets (number of bits to be stored) for partially-specified patterns to the test sets obtained from ATPG programs that attempt to generate compact test sets [9]. The motivation for generating small test sets is to reduce testing time. However, the high degree of compression obtained for partially-specified test sets demonstrates that test set compaction is not always necessary-the testing time is reduced more effectively by encoding partially-specified test sets. The proposed encoding method provides significant test set compression (over 10X) for many full-scan and non-scan circuits. The paper is organized as follows. In Section 2, we review twisted-ring counters and present our test set encoding method. As mentioned above, our encoding method is tailored towards the use of a TRC for test application. We describe our pattern application technique using TRCs and illustrate the method for a boundary scan architecture in which test responses are captured in a separate scan chain. In Section 3, we present experimental results for the ISCAS 85 [11] and

EMBEDDED CORE TESTING

ISCAS 89 [12] benchmark circuits. Section 4 presents the conclusions and outlines directions for further research.

2. TEST SET ENCODING AND PATTERN

DECOMPRESSION

In this section, we first review a recently-proposed BIST approach based on twisted-ring counters (TRCs). We then present a TRC-based test vector compression/decompression approach for embedded core testing. We describe the proposed test-per-clock pattern application technique using TRCs and illustrate the method for a boundary scan architecture in which test responses are captured in a separate scan chain. An n-bit ring counter is a group of n flip-flops F1, F2,..., Fn connected as a shift register, with the output of Fn fed back to the input of F1. It behaves as a counter with up to n distinct states depending on the initial value (seed). The TRC is a ring counter with an inverter added between the output of Fn and the input of F1. An n-bit TRC behaves as a counter with up to 2n distinct states depending on its seed. TRCs have recently been proposed for the design of BIST pattern generation circuits [6].

Test application in [6] is carried out by reconfiguring the input scan register of the circuit under test as a ring counter and a TRC. A small number of seed patterns are stored in a ROM, and for each seed, the pattern generator is clocked for 3n clock cycles. For the first n cycles, the pattern generator operates as a ring counter (shift mode) while for the remaining 2n cycles, it operates as a TRC (twist mode). A single 4-to-1 multiplexer is used to control the two-mode operation of the pattern generator. It was shown that a small number of seeds are generally sufficient to embed an arbitrary precomputed test set. The set of seeds may be viewed as an encoded test set, which is used to generate a superset of the precomputed test set

477

during test application. A key advantage of this approach is that test-per-clock BIST pattern application is achieved without requiring any mapping logic between the scan register flip-flops and the circuit under test. We now present another application of TRCs-test vector compression/decompression for embedded core testing that provides all the advantages of the method described in [6]. In addition, the proposed technique allows more efficient use of the TRC by removing a restriction that is inherent in the BIST architecture of [6], namely, the pattern generator can change modes (from shift to twist) only once for every seed. This restriction limits the number of patterns that can be generated from any starting state (seed) to 3n. We show in this paper that the entire precomputed test set can be generated from only one starting state if the pattern generator is allowed to switch modes freely, i.e., at any clock cycle. In fact, any test pattern can be generated from an arbitrarily chosen initial state in at most n cycles. This observation forms the basis for the test architecture proposed in the paper. Figure shows the main idea behind the pattern generator. The test set is encoded as a single-bit stream; during test application, each bit of the encoded test set determines the operation (shift or twist) to be performed during the corresponding clock cycle. The encoded test set is stored in tester memory and transferred to the IC serially during test application. For a precomputed test set Tz with m patterns, the size of the encoded test set TE is at most mn bits, which equals the storage requirement when no encoding is employed. However, we show later that the size of TE is generally much smaller than mn bits. Another advantage of using the set-up shown in Figure is that the patterns are applied in a test-per-clock fashion without adding delays on the functional logic paths. When no encoding is employed, i.e., TD is stored in the tester as in traditional testing, a total of m patterns are applied

The proposed method is test-per-clock with respect to the scan clock, as opposed to the at-speed functional clock.

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478

Input scan register

Multiplexer

Select

(encoded test set)

FIGURE

Core under test

Generic pattern application using a twisted-ring counter.

to the core under test in mn cycles (test-per-scan). However, with encoding, a total of el patterns are applied to the core under test in exactly ITel cycles. Therefore, even if no compression is achieved via encoding in the worst case, a total of mn patterns are applied in mn cycles. For example, consider the example To in Figure 2. We assume that TRC starts in the all-0 state. This can easily be achieved using a global reset. The encoded test set Te contains only 26 bits, a saving of 47%, both in tester memory and test application time. Furthermore, using this encoded test set, a total of 26 patterns are applied

to the core under test in 26 cycles, instead of the only 7 patterns that are applied in 49 cycles if To is stored in tester memory. The patterns from Tz that are applied to the core under test are highlighted in the figure. In general, it is not necessary to assume an all-0 initial state. Any initial state can be scanned into the TRC using the serial scan-in mechanism shown in the test architecture of Figure 3. In this paper, however, we assume that the TRC always starts in the all-0 state. It is straightforward to show that any test pattern can be generated from any given state S

IT

ooooooo

Initial state

0101011 1101010 1001101 0001110 1110001 011001 1110110

3 cycles

6 cycles

1110110 0001110

0000000

STT

TTSTTT

TSS 3 cycles

/r

010t011

S,s

4 cycles 5 cycles 1110001 0110011 STT$

TSTTT

2 cycle

An example TD

3 cycles

1101010 1001101 SST

000000 I00000 0110000 1011000 1101100 1110110 0111011 0011101

Size of TD

49 bits, size of TE

010101

ooo o I010101 101010 1000111 1100011

1110001 Encoded test set (symbolic): TTSTTTSTTTSSTSTTTSTTSSSSST Encoded test set (binary): t0111011100101 11011000

t0111000

/OOl lOO [ O01110 [1100111 ]0110011 /i011001 /0101100 /I010110

010011010 10101 1001101

Test patterns applied to core under test

26 bits.

FIGURE 2 An example illustrating test set encoding and pattern application (T and S refer to twist and shift, respectively).

EMBEDDED CORE TESTING

[1

Scan in

479

Multiplexer

Scan enebte Core under test

Serial test data from tester (encoded)

FIGURE 3 Proposed pattern application scheme using a TRC.

of an n-bit pattern generator (Fig. 1) in at most n cycles. Let t-tit2.. "tn and S=SlS2"’’Sn. Then we can generate from s in a minimum number of cycles by determining the smallest integer r such that sl=tr+l, s2=tr+2,...,Sn-r=tn The test pattern can then be generated from s in exactly r cycles. Intuitively, this also implies that the TRC can always be made to generate any desired test pattern by "flushing out" s and carefully reloading the bits corresponding to t. A block diagram of the interface between the ATE and the SOC under test is shown in Figure 4.

The tester supplies patterns with frequency fext, Ays is the functional clock (system) frequency, and fcan is the scan clock frequency. Since a pattern is applied to the core every cycle, fsoan=fext. The on-chip clock generator is used to generate a synchronization clock to control the flow of data between ATE and the SOC, and to synchronize fext with fsan. We introduce the term test rate for external testing to measure the number of patterns that are applied to the core under test per second. The test rate is simply fscan for the TRC-based architecture. We also use the term relative test rate

SOC

ATE

fsca fext

Wrapper

Cre,

I/O

channel

ATE

fsca fext

Wrapper Core

External

Sync.

On-chip clock generator

fsys’fscan Sync. Clock FIGURE 4 A conceptual architecture for testing a system-on-a-chip.

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to measure the number of patterns applied to the core under test per tester cycle. For the pattern application scheme in Figure 3, the relative test rate is the maximum value possible, i.e., 1. Note that for a test-per-scan scheme, the test rate is only fscan/n and the relative test rate is only 1/n. Let amn be the size of the encoded test set Te. In other words, a ]Tel/[ TD[ is directly proportional to the amount of compression achieved using the pro-

posed encoding method. Test-per-clock pattern application is therefore achieved using a TRC without adding any additional logic on the critical paths between the flipflops and the inputs of the core under test. Hence, as in test-per-scan methods [14, 15], the proposed method imposes no additional performance degradation beyond scan. This is in contrast to most test-per-clock methods, which require mapping logic between the flip-flops and the circuit under test. Furthermore, the test-per-clock approach allows us to use slower, low-cost testers. For example, in order to apply all the test patterns in time T, a test-per-scan method requires the tester to run at frequency such that fscan--mn/T. With our test-per-clock approach, the testing can be carried out in the same amount of time using a tester that runs at frequency such that fca amn/ T. Moreover, an additional re(an- 1) patterns are applied to the circuit in the same amount of time. This increases the likelihood of detecting nonmodeled faults that are not explicitly targeted by

Tz. As in any test-per-clock approach, response monitoring in the proposed method must be done every tester clock cycle. This can be carried out using a combination of space compaction [16, 17] and multiple-input signature register. The response monitoring logic can be designed from the responses of the core under test to the patterns in To and to the additional patterns that are applied by the TRC. We now address the issue of determining the encoded test set Te from the given precomputed test set To. We first note that for full-scan cores, since the patterns can be reordered, the encoding

problem can be formulated as the well-known traveling salesman problem (TSP) on a weighted directed graph. Every pattern in To corresponds to a node in a directed graph G. An additional node s in this graph corresponds to the all-0 initial state of the pattern generator. The weight of an edge (x, y) in G equals the minimum number of cycles required to generate Y=YlYz"’Yn from x--xlx2." "xn. This is determined from the smallest r _< n such that xl yr + 1, x2 yr + 2, Xn- y,,.

It can now be easily seen that the minimum-size encoding of To corresponds to a minimum-cost Hamiltonian path (TSP) in G that starts at s. Since the traveling salesman problem is NPcomplete [10], we use a simple greedy algorithm to carry out the encoding. Starting from the all-0 initial state S, we generate the pattern in To that is at the least "distance" from S. (The distance of y from x is given by the weight of the edge from x to y in G.) We then continue this process until all the patterns in To have been generated. Figure 2 illustrates the greedy algorithm for an example test set. The complexity of this algorithm is O(m2), and the complexity of generating the graph is

O(man). The encoding algorithm can also be applied to test sets containing partially-specified patterns (test cubes). In fact, significantly more compression can be expected if To is partially-specified. In order to illustrate the encoding for test cubes, we introduce the notion of compatibility between the bits xi and yj of test cubes x and y. We define xi and yj to be compatible if either (i) both xi and y are specified and equal, or (ii) at least one of these two bits is a don’t care. Once again, we start from the all-0 s initial state and follow a greedy strategy of choosing a pattern at the least distance, i.e., a node in G connected by an outgoing edge from s with the least weight. The weight w(x,y) of the edge from x to y is determined as follows: w(x,y)= r, where r is the smallest integer such that xi and y +i are compatible, 1 _ l/n, since the size of the encoded test set is at least m bits. Quite remarkably, this lower bound is nearly achieved for several circuits in Table III. For example, for s344 and s349, the lower bound on a is 0.0417. Using the Mintest test sets, we obtain a-0.0437 and 0.0494, respectively.

TABLE II Comparison of TRC-based pattern generation for completely-specified Atalanta test sets with test-perscan method of [5]

Test per scan [5]

Proposed method

Circuit

rn

a

IZl

Testing time (cycles)

c432 c499 c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552

49 53 53 84 144 103 179 122 40 215

0.84 0.87 0.93 0.85 0.79 0.97 0.86 0.95 0.86 0.96

1489 !898 2956 2930 3791 23279 7678 20775 1100 42952

1489 1898 2956 2930 3791 23279 7678 20775 1100 42952

No. of patterns applied

m

ITel

(cycles)

No. of patterns applied

1489 1898 2956 2930 3791 23279 7678 20775 1100 42952

59 58 80 103 130 133 198 214 36 271

1608 1449 3930 2910 3159 24405 7752 30501 912 42528

1608 1449 3930 2910 3159 24405 7752 30501 912 42528

59 56 80 103 130 133 198 214 36 271

Testing time

A. CHANDRA et al.

484

TABLE III Experimental results (test-per-clock) for partially-specified test sets Atalanta test sets

Mintest test sets

No. of bits

Amount of

No. of bits

Amount of

stored for

test data

stored for

proposed encoding

obtained using ATPG compaction

proposed encoding

test data obtained

method

Circuit

m

c432 c499 c880 c1355 c1908 c2670 c3540 c6288 c5315 c7552 s208 s298 s344 s349 s382 s386 s400 s420 s444 s510 s526 s641 s713 s820 s832 s838 s953 s1196 s1238 s1423 s1488 s1494 s5378 s9234 s13207 s15850

128 93 355 143 434 639

0.3273 0.3913 0.2605 0.8136 0.6919 0.2652

39483

201 1213 845 64 93 85 85 102 102 96 129 107 103 160 200 192 195 199 257 227 291 164 89 252 250

0.5176 0.3094 0.5030 0.2459 0.0981 0.1746 0.1697 0.1336 0.3824 0.1225 0.2012 0.1036 0.2804 0.1857 0.0987 0.1396 0.2973 0.2740 0.1456 0.1513 0.1773 0.1916 0.1334 0.4159 0.2666

3329 66789 87929 299 155 356 346 327 507 289 908 266 722 713 1065 1447 1333 1254 2506 1545 1651 1005 1080 1467 933

1508 1492 5548 4770 9909

1764 2173 3180 3444 4752 23999 1280 21716 44505

4. CONCLUSIONS

We have presented a novel test vector compression method and decompression architecture for embedded core testing. These are based on the use of a twisted-ring counter, which can operate in both the shift and twist modes. The serial bit stream

m

a

211 114 406 198 262 775 891 202 1552 1133 81 127 129 126 118 120

0.2387 0.6569 0.1676 0.6327 0.5749 0.1874 0.1306 0.5680 0.2018 0.2929 0.1391 0.0649 0.0437 0.0494 0.1035 0.2231 0.0796 0.1321 0.0889 0.0687 0.1045 0.1395 0.1398 0.1219 0.1252 0.1265 0.1309 0.3196 0.3431 0.1285 0.1370 0.1282 0.0827 0.1584 0.0634 0.0779

120 161 128 130 207 231 220 253 255 319 255 346 360 524 317 311 1459 1929 3237 3290

method 1813 3070 4082 5136 4970 33839 5818 3671 55748 68694 214 140 135 149 293 348 229 744 273 223 519 1740 1661 709 734 2703 1502 3539 3953 6127 608 558 25821 75471 143658 156593

using ATPG compaction 972 2132 640 3444 3498 10252 4203 384 6586 15111 513 391 312 552 600 819 576 1505 576 1350 1176 1134 1134 2139 2162 5025 3420 3616 3872 1820 1414 1400 20758 25935 163800 58045

that controls the operation of the counter comprises the encoded test set. The proposed method offers a number of important advantages- significant test compression (over 10X in many cases), less tester memory and reduced testing time, the ability to use a slow tester without compromising test quality or testing time, and

EMBEDDED CORE TESTING

no performance degradation for the core under

test. The decompressed patterns are applied test-perclock, thereby applying a large number of patterns to the core under test and increasing the likelihood of detecting non-modeled faults. Experimental resuits for the ISCAS benchmark circuits demonstrate that the proposed test architecture offers an attractive solution to the problem of achieving high test quality and low testing time with relatively slower, low-cost testers. The experimental results also show that the encoded test sets obtained from partially-specified test sets (test cubes) are often smaller than the compacted test sets generated by automatic test pattern generation programs. The proposed scheme has a limitation that it can be only applied to register based designs such as the designs which employ built-in logicblock observation (BILBO) registers.

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[11] Brglez, F. and Fujiwara, H. (1985). A neutral netlist of 10 combinational benchmark circuits and a target simulator in Fortran, Proc. International Symposium on Circuits and

Systems, pp. 695-698. [12] Brglez, F., Bryan, D. and Kozminski, K. (1989).

[13]

[14]

[15]

[16]

[17]

"Combinational profiles of sequential benchmark circuits", Proc. 1989 lnt. Symposium on Circuits and Systems, pp. 1929-1934. Lee, H. K. and Ha, D. S., "On the Generation of Test Patterns for Combinational Circuits", Tech. Rep. No. 12_93, Dept. of Electrical Eng., Virginia Poly. Institute and State Univ. Rajski, J., Tyszer, J. and Zacharia, N. (1998). "Test data decompression for multiple scan designs with boundary scan", IEEE Transactions on Computers, 47(11), 1188-1200. Zacharia, N., Rajski, J., Tyszer, J. and Waicukauski, J. A. (1996). "Two-dimensional test data decompressor for multiple scan designs", Proc. International Conference, pp. 186-194. Chakrabarty, K., Murray, B. T. and Hayes, J. P. (1998). "Optimal zero-aliasing space compaction of test responses", IEEE Transactions on Computers, 47(11), 1171-1187. Savir, J., "Shrinking wide compressors", IEEE Transactions on Computer-Aided Design, 14, 1379-1387, Nov., 1995.

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embedded-core based system chips", Proc. International Test Conference, pp. 130 143. Immaneni, V. and Raman, S. (1990). "Direct access test scheme-design of block and core cells for embedded ASICs", Proc. 1990 International Test Conference, pp. 488-492. Cheng, K.-T. and Lin, C.-J. (1995). "Timing-driven test point insertion for full-scan and partial-scan BIST", Proc. 1995 International Test Conference, pp. 506-514. Fagot, C., Girard, P. and Landrault, C. (1997). "On using machine learning for logic BIST", Proc. International Test Conference, pp. 338-346. Jas, A. and Touba, N. A. (1998). "Test vector decompression via cyclical scan chains and its application to testing core-based designs", Proc. International Test Conference, pp. 458-464. Chakrabarty, K., Murray, B. T. and Iyengar, V. (1999). "Built-in test pattern generation for high performance circuits using twisted-ring counters", Proc. VLSI Test Symposium, pp. 22-27. http://notes.sematech.org/97pelec.htm, The National Technology Roadmap for Semiconductors (NTRS), Silicon Industry Association (SIA), 1997. Agrawal, V. D. and Chakraborty, T. J. (1995). "Highperformance circuit testing using slow-speed testers", Proc. International Test Conference, pp. 302-310. Hamzaoglu, I. and Patel, J. H. (1998). "Test set compaction algorithms for combinational circuits", Proc. International Conference on CAD, pp. 283-289. Garey, M. S. and Johnson, D. S. (1979). Computers and Intractability: A Guide to the Theory of NP-Completeness, Freeman, W. H. and Company, New York.

Authors’ Biographies Anshuman Chandra received the B.E. degree in Electrical engineering from the University of Roorkee, Roorkee, India, in 1998, M.S. degree in Electrical and Computer Engineering from Duke University, Durham, USA, in 2000, and is currently enrolled in the Ph.D. program at Duke University. His research interests are in the fields of VLSI Design, Digital Testing and Computer Architecture. He is a recipient of TTTC James Beausang Student Paper award for DFT for a paper published in Proc. 2000 IEEE FLSI Test Symposium. He is currently working in the areas of test set compression/decompression, embedded core testing and built-in self test (BIST). He is a

student member of IEEE. Krishnendu Chakrabarty received the B. Tech. degree from the Indian Institute of Technology, Kharagpur, in 1990, and the M.S.E. and Ph.D.

degrees from the University of Michigan, Ann Arbor, in 1992 and 1995, respectively, all in Computer Science and Engineering. He is now Assistant Professor of Electrical and Computer

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Engineering at Duke University. Dr. Chakrabarty is a recipient of the National Science Foundation’s Early Faculty (CAREER) award, the office of Naval Research Young Investigator Award and the Mercator Professor award from the Deutsche Forschungsgemeinschaft, Germany for carrying out research at the University of Potsdam during 2000-2001. His current research projects (supported by NSF, ONR, DARPA and industrial sponsors) are in system-on-a-chip test, embedded real-time operating systems, distributed sensor networks, and architectural optimization of microelectrofluidic systems. He has published over 65 papers in archival journal and refereed conference proceedings, and he holds a US patent in built-in self-test. He is a senior member of IEEE, member

of Sigma Xi, serves as Vice Chair of Technical Activities in IEEE’s Test Technology Technical Council, and is a member of the program committees of several IEEE/ACM conferences and workshops. Mark C. Hansen supervises the IC Design Automation Operations groups at Delphi Delco Electronics Systems in Kokomo, Indiana. His research interests include functional-level fault modeling, design for test, ATPG, BIST, and analog test. He holds a dozen patents. Hansen received a BSEE from Michigan State University, and MSEE from Carnegie Mellon University, and a Ph.D. in Computer Science and Engineering from University of Michigan, Ann Arbor. He is a member of the IEEE and the IEEE Computer Society.